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miaobiao
- 基于VHDL环境下的秒表设计源代码 很好用的-Environment based on VHDL design source code stopwatch good use
run_watch
- 提供一个数字秒表的EDA设计实例,内故有VHDL源代码,并有运行仿真图。-To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.
PlayDemo
- VC写的h.264规范解码程序,具体看程序注释-VC norms h.264 decoding written procedures, specific procedures see Notes
stopwatch
- 基于fpga的停表设计vudl编写,使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
KESHE
- 基于FPGS的数字秒表设计文件 含有计时,停止,复位,清零功能-FPGS-based digital stopwatch design document contains a time, stop, reset, Clear Function
VHDL312vh6
- 包含若干个VHDL小例子,有交通灯,电子琴,简易秒表,等等,交通灯已经测试过,根据自己的需要,稍微改动,很好用!-VHDL contains a number of small example, there is traffic lights, Electronic organ, simple stopwatch, and so on, traffic lights have been tested, according to their own needs, slightly altered,
paobiao
- 一个基于FPGA的数字跑表系统的设计,最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
sheji2
- 一个秒表的硬件设计,学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
stopwatch
- 一个用VHDL编写的秒表程序,可用Max+PlusII仿真-Prepared by a stopwatch with VHDL procedures, Max+ PlusII simulation can be used
Stopwatchprecisiondesign
- 高精度秒表设计,VHDL语言设计,课程设计,word版-Stopwatch precision design, VHDL language design, curriculum design, word version
miaobiao
- 秒表功能,自带工程,EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
VHDlclock
- 数字秒表的VHDL课程设计 通过硬件测试 精确到ms 最大可计时为24小时 -Digital stopwatch curriculum design through the VHDL hardware testing is accurate to ms maximum time of 24 hours
watch
- VHDL编写的秒表,经过试验了,用的应该还可以-VHDL stopwatch prepared, tested, and can be used
EXP4_sec
- 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0,当计数到9时,下一次数值为0。利用Verilog HDL语言,编程实现上述功能。-Stopwatch
Multichanneldataacquisition
- 多路数据采集,包括八路数据模拟电压测量,计数器,99秒马表-Multi-channel data acquisition, including the eight-way analog voltage measurement data, counters, 99 seconds stopwatch
time
- 电子钟实现 包含数字跑表 万年历 设置三个闹钟 时间,日期调整-Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust
e7v4
- 数字钟:显示,设置时间,设置闹铃(报时),秒表。 平台:quartusII 5.1。 说明:此版本中已将系统时钟调快,自己稍微改动一下即可,小小的考验,做出来会更有成就感!-digital clock:display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
vhd_design
- 我学习VHDL的课程设计,是多功能数字钟,有闹钟,秒表等功能,多指教-I learned VHDL course design is multi-functional digital clock, there is an alarm clock, stopwatch functions, multi-Zhi Jiao
clock
- 采用Verilog HDL语言编写的多功能数字钟,包括四个功能:时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
clock
- 秒表的verilog语言实现,个人课程设计代码,已验证!实现显示秒,分,时暂停,修正等功能。-Stopwatch' s verilog language implementation, personal curriculum design, code, and has been verified! Implementation show seconds, minutes, suspended, amendment and other functions.